Hitachi SH7750 Programming Manual page 273

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FIPR(int m,n)
{
if(FPSCR_PR == 0) {
pc += 2;
clear_cause();
fipr(m,n);
}
else
undefined_operation();
}
Possible Exceptions:
• Invalid operation
• Overflow
• Underflow
• Inexact
/* FIPR FVm,FVn */
Rev. 2.0, 03/99, page 259 of 396

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