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10.47
FTRV
Vector
Transformation
PR
Format
FTRV XMTRX,FVn XMTRX*FVn → FVn
0
1
—
Description
When FPSCR.PR = 0: This instruction takes the contents of floating-point registers XF0 to XF15
indicated by XMTRX as a 4-row × 4-column matrix, takes the contents of floating-point registers
FR[n] to FR[n + 3] indicated by FVn as a 4-dimensional vector, multiplies the array by the vector,
and stores the results in FV[n].
XMTRX
XF[0]
XF[4]
XF[1]
XF[5]
XF[2]
XF[6]
XF[3]
XF[7]
The FTRV instruction is intended for speed rather than accuracy, and therefore the results will
differ from those obtained by using a combination of FADD and FMUL instructions. The FTRV
execution sequence is as follows:
1. Multiplies all terms. The results are 30 bits long.
2. Aligns these results, rounding them to fit within 28 bits.
3. Adds the aligned values.
4. Performs normalization and rounding.
Special processing is performed in the following cases:
1. If an input value is an sNaN, an invalid exception is generated.
2. If the input values to be multiplied include a combination of 0 and infinity, an invalid
operation exception is generated.
3. In cases other than the above, if the input values include a qNaN, the result will be a qNaN.
4. In cases other than the above, if the input values include infinity:
a. If multiplication results in two or more infinities and the signs are different, an invalid
exception will be generated.
b. Otherwise, correct infinities will be stored.
Rev. 2.0, 03/99, page 292 of 396
Floating-point
TRansform Vector
Summary of Operation Instruction Code
—
XF[8]
XF[12]
XF[9]
XF[13]
XF[10]
XF[14]
XF[11]
XF[15]
1111nn0111111101 4
—
FVn
FVn
FR[n]
×
→
FR[n+1]
FR[n+2]
FR[n+3]
Floating-Point Instruction
Execution
States
—
FR[n]
FR[n+1]
FR[n+2]
FR[n+3]
T Bit
—
—
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