Table of Contents
Advertisement
Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL,
FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3
(g).
If an executing instruction locks any resource—i.e. a function block that performs a basic
operation—a following instruction that happens to attempt to use the locked resource must be
stalled (figure 8.3 (h)). This kind of stall can be compensated by inserting one or more instructions
independent of the locked resource to separate the interfering instructions. For example, when a
load instruction and an ADD instruction that references the loaded value are consecutive, the 2-
cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software
performance can be improved by such instruction scheduling.
Other penalties arise in the event of exceptions or external data accesses, as follows.
• Instruction TLB miss: a penalty of 7 CPU clocks
• Instruction access to external memory (instruction cache miss, etc.)
• Data access to external memory (operand cache miss, etc.): a penalty of 2 CPU clocks + 3 bus
clocks
• Data access to a memory-mapped control register. The penalty differs from register to register,
and depends on the kind of operation (read or write), the clock mode, and the bus use
conditions when the access is made.
During the penalty cycles of an instruction TLB miss or external instruction access, no instruction
is issued, but execution of instructions that have already been issued continues. The penalty for a
data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted
until the arrival of the requested data. The number of penalty cycles for instruction and data
accesses is largely dependent on the user's memory subsystems.
Rev. 2.0, 03/99, page 162 of 396
Advertisement
Table of Contents
