Exception Flow - Hitachi SH7750 Programming Manual

Table 5.2 Exceptions (cont)
Exception Execution
Category Mode
Interrupt Completion
type
Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest
number represents the highest priority).
Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in
other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3–IRL0).
Module/source: See the sections on the relevant peripheral modules.
Notes: 1. When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.
2. The priority order of external interrupts and peripheral module interrupts can be set by
software.
5.5

Exception Flow

5.5.1 Exception Flow
Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and
exception handling. For the sake of clarity, the following description assumes that instructions are
executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different
kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an
exception are shown only for SSR, SPC, EXPEVT/INTEVT, SR, and PC, but other registers may
be set automatically by hardware, depending on the exception. For details, see section 5.6,
Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for
exception handling during execution of a delayed branch instruction and a delay slot instruction,
and in the case of instructions in which two data accesses are performed.
Rev. 2.0, 03/99, page 88 of 396
Exception
Peripheral DMAC
module
interrupt
(module/
source)
SCIF
Priority Priority
Level Order
DMTE0 4 *2
DMTE1
DMTE2
DMTE3
DMAE
ERI
RXI
BRI
TXI
Vector
Address Offset
(VBR) H'600
Exception
Code
H'640
H'660
H'680
H'6A0
H'6C0
H'700
H'720
H'740
H'760