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9.1.2
Register Configuration
Table 9.2 shows the registers used for power-down mode control.
Table 9.2
Power-Down Mode Registers
Name
Standby control register
Standby control register 2 STBCR2
9.2
Register Descriptions
9.2.1
Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the
power-down mode status. It is initialized to H'00 by a power-on reset via the
watchdog timer overflow.
Bit:
Initial value:
R/W:
Bit 7—Standby (STBY): Specifies a transition to standby mode.
Bit 7: STBY
0
1
Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of
peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module
related pins go to the high-impedance state in standby mode.
For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control.
Bit 6: PHZ
0
1
Abbreviation
STBCR
7
6
STBY
PHZ
PPU
0
0
R/W
R/W
R/W
Description
Transition to sleep mode on execution of SLEEP instruction
Transition to standby mode on execution of SLEEP instruction
Description
Peripheral module related pins are in normal state
Peripheral module related pins go to high-impedance state
Initial
R/W
Value
P4 Address
R/W
H'00
H'FFC00004 H'1FC00004
R/W
H'00
H'FFC00010 H'1FC00010
5
4
3
MSTP4
MSTP3
0
0
0
R/W
R/W
Area 7
Address
pin or due to
2
1
MSTP2
MSTP1
0
0
R/W
R/W
(Initial value)
(Initial value)
Rev. 2.0, 03/99, page 179 of 396
Access
Size
8
8
0
MSTP0
0
R/W
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