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4.1.2
Register Configuration
Table 4.2 shows the cache control registers.
Table 4.2
Cache Control Registers
Name
Cache control
register
Queue address
control register 0
Queue address
control register 1
Notes: 1. The initial value is the value after a power-on or manual reset.
2. This is the address when using the virtual/physical address space P4 area. When
making an access from physical address space area 7 using the TLB, the upper 3 bits
of the address are ignored.
4.2
Register Descriptions
There are three cache and store queue related control registers, as shown in figure 4.1.
CCR
31
QACR0
31
QACR1
31
indicates reserved bits: 0 must be specified in a write; the read value is undefined.
Rev. 2.0, 03/99, page 62 of 396
Abbreviation R/W
CCR
R/W
QACR0
R/W
QACR1
R/W
Figure 4.1 Cache and Store Queue Control Registers
Initial
P4
1
Value*
Address*
H'0000 0000 H'FF00 001C
Undefined
H'FF00 0038
Undefined
H'FF00 003C
16 15
14
12 11 10 9 8 7 6 5 4 3 2
IIX
ICI ICE
Area 7
2
2
Address*
H'1F00 001C
H'1F00 0038
H'1F00 003C
1 0
CB
OIX
ORA
OCI
WT OCE
5 4
2 1 0
AREA
5 4
2 1 0
AREA
Access
Size
32
32
32
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