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• OCI: OC invalidation bit
When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always
returns 0 when read.
• CB: Copy-back bit
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
• WT: Write-through bit
Indicates the P0, U0, and P3 area cache write mode. When address translation is performed,
the value of the WT bit in the page management information has priority.
0: Copy-back mode
1: Write-through mode
• OCE: OC enable bit
Indicates whether or not the OC is to be used. When address translation is performed, the OC
cannot be used unless the C bit in the page management information is also 1.
0: OC not used
1: OC used
(2) Queue Address Control Register 0 (QACR0): Longword access to QACR0 can be
performed from H'FF00 0038 in the P4 area and H'1F00 0038 in area 7. QACR0 specifies the area
onto which store queue 0 (SQ0) is mapped when the MMU is off.
(3) Queue Address Control Register 1 (QACR1): Longword access to QACR1 can be
performed from H'FF00 003C in the P4 area and H'1F00 003C in area 7. QACR1 specifies the
area onto which store queue 1 (SQ1) is mapped when the MMU is off.
Rev. 2.0, 03/99, page 64 of 396
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