Frchg - Hitachi SH7750 Programming Manual

10.41

FRCHG

FR Bit
Inversion
PR Format
0 FRCHG
1 —
Description
This instruction inverts the FR bit in floating-point register FPSCR. When the FR bit in FPSCR is
changed, FR0 to FR15 in FPPR0 to FPPR31 become XR0 to XR15, and XR0 to XR15 become
FR0 to FR15. When FPSCR.FR = 0, FPPR0 to FPPR15 correspond to FR0 to FR15, and FPPR16
to FPPR31 correspond to XR0 to XR15. When FPSCR.FR = 1, FPPR16 to FPPR31 correspond to
FR0 to FR15, and FPPR0 to FPPR15 correspond to XR0 to XR15.
Operation
void FRCHG()
{
if(FPSCR_PR == 0){
FPSCR ^= 0x00200000; /* bit 21 */
PC += 2;
}
else undefined_operation();
}
Possible Exceptions:
None
FR-bit CHanGe
Summary of Operation
FRSCR.FR=~FRSCR.FR
—
/* FRCHG */
Floating-Point Instruction
Instruction Code
1111101111111101 1
—
Rev. 2.0, 03/99, page 281 of 396
Execution
States T Bit
—
— —