Sts - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.94

STS

Store from FPU
System Register
Format
STS
FPUL,Rn
STS
FPSCR,Rn
STS.L FPUL,@-Rn
STS.L FPSCR,@-Rn
Description
This instruction stores FPU system register FPUL or FPSCR in the destination.
Operation
STS(int n, int *FPUL)
{
R[n]= *FPUL;
PC+=2;
}
STS_SAVE(int n, int *FPUL)
{
R[n]-=4;
Write_Long(R[n],*FPUL) ;
PC+=2;
}
STS(int
n)
{
R[n]=FPSCR&0x003FFFFF;
PC+=2;
}
STS_RESTORE(int
{
R[n]-=4;
Write_Long(R[n],FPSCR&0x003FFFFF)
STore from FPU
System register
Summary of Operation
FPUL → Rn
FPSCR → Rn
Rn-4 → Rn, FPUL → (Rn)
Rn-4 → Rn, FPSCR → (Rn) 0100nnnn01100010 1
/* STS FPUL,Rn
/* STS.L FPUL,@-Rn
/* STS FPSCR,Rn
n)
/* STS.L FPSCR,@-Rn
System Control Instruction
Instruction Code
0000nnnn01011010 1
0000nnnn01101010 1
0100nnnn01010010 1
*/
*/
*/
*/
Rev. 2.0, 03/99, page 375 of 396
Execution
States
T Bit

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