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5.6
Description of Exceptions
The various exception handling operations are described here, covering exception sources,
transition addresses, and processor operation when a transition is made.
5.6.1
Resets
(1) Power-On Reset
• Sources:
SCK2 pin high level and
When the watchdog timer overflows while the WT/
cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
• Transition address: H'A000 0000
• Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections. For some CPU functions, the
must be driven low. It is therefore essential to execute a power-on reset and drive the
pin low when powering on.
Power_on_reset()
{
EXPEVT = H'00000000;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD=0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A0000000;
}
Rev. 2.0, 03/99, page 92 of 396
pin low level
bit is set to 1 and the RSTS bit is
pin and
pin
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