Hitachi SH7750 Programming Manual page 165

1. 1-step operation: 1 issue cycle
EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*,
DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#,
ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT,
LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS,
single-/double-precision FABS/FNEG
D
I
2. Load/store: 1 issue cycle
MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR
D
I
3. GBR-based load/store: 1 issue cycle
MOV.[BWL]@(d,GBR)
D
I
4. JMP, RTS, BRAF: 2 issue cycles
D
I
5. TST.B: 3 issue cycles
D
I
6. AND.B, OR.B, XOR.B: 4 issue cycles
D
I
7. TAS.B: 5 issue cycles
D
I
8. RTE: 5 issue cycles
D
I
9. SLEEP: 4 issue cycles
D
I
Figure 8.2 Instruction Execution Patterns
EX S
NA
EX S
MA
SX S
MA
EX S
NA
D
EX
NA
SX S
MA
D
SX
NA
SX
D
SX S
MA
D
SX
NA
SX
D
D
EX S
MA
D
EX
MA
D EX
D
EX S
NA
D
EX
NA
EX
D
D
EX S
NA
D
EX
NA
EX
D
D
S
S
S
NA
S
NA S
SX S
MA
S
S
NA
EX NA S
D EX
MA
S
NA S
EX
NA S
EX
D NA
S
NA S
EX
NA S
Rev. 2.0, 03/99, page 151 of 396
S
S