Ocbp - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.71

OCBP

Cache Block Purge
Format
OCBP @Rn
Description
This instruction accesses data using the contents indicated by effective address Rn. If the cache is
hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to
external memory and that block is invalidated (the V bit is cleared to 0). If there is no unwritten
information (U bit = 0), the block is simply invalidated. No operation is performed in the case of a
cache miss or an access to a non-cache area.
Operation
OCBP(int n)
{
if(is_dirty_block(R[n]))
invalidate_operand_cache_block(R[n]);
PC+=2;
}
Possible Exceptions:
• Data TLB miss exception
• Data TLB protection violation exception
• Address error
Note that the above exceptions are generated even if OCBP does not operate.
Rev. 2.0, 03/99, page 340 of 396
Operand Cache Block
Purge
Summary of Operation
Operand cache block purge 0000nnnn10100011 1
/* OCBP @Rn */
write_back(R[n])
Data Transfer Instruction
Instruction Code
Execution
States
T Bit

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