Hitachi SH7750 Programming Manual page 203

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Error( char *er );
Error display function
These are floating-point number definition statements.
#define PZERO
#define NZERO
#define DENORM
#define NORM
#define PINF
#define NINF
#define qNaN
#define sNaN
#define EQ
#define GT
#define LT
#define UO
#define INVALID
#define FADD
#define FSUB
#define CAUSE
#define SET_E
#define SET_V
#define SET_Z
#define SET_O
#define SET_U
#define SET_I
#define ENABLE_VOUI 0x00000b80
#define ENABLE_V
#define ENABLE_Z
#define ENABLE_OUI
#define ENABLE_I
#define FLAG
#define FPSCR_FR
#define FPSCR_PR
#define FPSCR_DN
0
1
2
3
4
5
6
7
0
1
2
3
4
0
1
0x0003f000
/* FPSCR(bit17-12) */
0x00020000
/* FPSCR(bit17) */
0x00010040
/* FPSCR(bit16,6) */
0x00008020
/* FPSCR(bit15,5) */
0x00004010
/* FPSCR(bit14,4) */
0x00002008
/* FPSCR(bit13,3) */
0x00001004
/* FPSCR(bit12,2) */
/* FPSCR(bit11,9-7) */
0x00000800
/* FPSCR(bit11) */
0x00000400
/* FPSCR(bit10) */
0x00000380
/* FPSCR(bit9-7) */
0x00000080
/* FPSCR(bit7) */
0x0000007C
/* FPSCR(bit6-2) */
FPSCR>>21&1
FPSCR>>19&1
FPSCR>>18&1
Rev. 2.0, 03/99, page 189 of 396

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