Hitachi SH7750 Programming Manual page 114

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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(4) Data TLB Protection Violation Exception
• Source: The access does not accord with the UTLB protection information (PR bits) shown
below.
PR
Privileged Mode
00
Only read access possible
01
Read/write access possible
10
Only read access possible
11
Read/write access possible
• Transition address: VBR + H'0000 0100
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR.
Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Data_TLB_protection_violation_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
EXPEVT = read_access ? H'000000A0 : H'000000C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 2.0, 03/99, page 100 of 396
User Mode
Access not possible
Access not possible
Only read access possible
Read/write access possible

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