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The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-
byte data (16 instructions).
• Tag
Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached.
The tag is not initialized by a power-on or manual reset.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
• Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
4.4.2
Read Operation
When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
•
If the tag matches and the V bit is 1
•
If the tag matches and the V bit is 0
•
If the tag does not match and the V bit is 0
•
If the tag does not match and the V bit is 1
3a. Cache hit
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
3b. Cache miss
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
→ (3a)
→ (3b)
→ (3b)
→ (3b)
Rev. 2.0, 03/99, page 73 of 396
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