Sts - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.93

STS

Store from
System Register
Format
STS
MACH,Rn
STS
MACL,Rn
STS
PR,Rn
STS.L MACH,@-Rn
STS.L MACL,@-Rn
STS.L PR,@-Rn
Description
This instruction stores system register MACH, MACL, or PR in the destination.
Operation
STSMACH(int n)
{
R[n]=MACH;
PC+=2;
}
STSMACL(int n)
{
R[n]=MACL;
PC+=2;
}
STSPR(int n)
{
R[n]=PR;
PC+=2;
}
STSMMACH(int n)
{
STore System register
Summary of Operation
MACH → Rn
MACL → Rn
PR → Rn
Rn-4 → Rn, MACH → (Rn)
Rn-4 → Rn, MACL → (Rn)
Rn-4 → Rn, PR → (Rn)
/* STS MACH,Rn */
/* STS MACL,Rn */
/* STS PR,Rn */
/* STS.L MACH,@-Rn */
System Control Instruction
Instruction Code
0000nnnn00001010 1
0000nnnn00011010 1
0000nnnn00101010 1
0100nnnn00000010 1
0100nnnn00010010 1
0100nnnn00100010 1
Rev. 2.0, 03/99, page 373 of 396
Execution
States
T Bit

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