Stc - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.92

STC

Store from Control Register
Format
STC
SR, Rn
STC
GBR, Rn
STC
VBR, Rn
STC
SSR , Rn
STC
SPC, Rn
STC
SGR, Rn
STC
DBR , Rn
STC
R0_BANK, Rn
STC
R1_BANK, Rn
STC
R2_BANK, Rn
STC
R3_BANK, Rn
STC
R4_BANK, Rn
STC
R5_BANK, Rn
STC
R6_BANK, Rn
STC
R7_BANK, Rn
STC.L SR, @-Rn
STC.L GBR, @-Rn
STC.L VBR, @-Rn
STC.L SSR, @-Rn
STC.L SPC, @-Rn
STC.L SGR, @-Rn
STC.L DBR, @-Rn
STC.L R0_BANK, @-Rn Rn-4 → Rn, R0_BANK → (Rn)
STC.L R1_BANK, @-Rn Rn-4 → Rn, R1_BANK → (Rn)
STC.L R2_BANK, @-Rn
STC.L R3_BANK, @-Rn
STC.L R4_BANK, @-Rn
STC.L R5_BANK, @-Rn
STC.L R6_BANK, @-Rn
STC.L R7_BANK, @-Rn
Rev. 2.0, 03/99, page 368 of 396
STore Control register
Summary of Operation
SR → Rn
GBR → Rn
VBR → Rn
SSR → Rn
SPC → Rn
SGR → Rn
DBR → Rn
R0_BANK → Rn
R1_BANK → Rn
R2_BANK → Rn
R3_BANK → Rn
R4_BANK → Rn
R5_BANK → Rn
R6_BANK → Rn
R7_BANK → Rn
Rn-4 → Rn, SR → (Rn)
Rn-4 → Rn, GBR → (Rn)
Rn-4 → Rn, VBR → (Rn)
Rn-4 → Rn, SSR → (Rn)
Rn-4 → Rn, SPC → (Rn)
Rn-4 → Rn, SGR → (Rn)
Rn-4 → Rn, DBR → (Rn)
Rn-4 → Rn, R2_BANK → (Rn)
Rn-4 → Rn, R3_BANK → (Rn)
Rn-4 → Rn, R4_BANK → (Rn)
Rn-4 → Rn, R5_BANK → (Rn)
Rn-4 → Rn, R6_BANK → (Rn)
Rn-4 → Rn, R7_BANK → (Rn)
System Control Instruction
(Privileged Instruction)
Instruction Code
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0000nnnn00110010
0000nnnn01000010
0000nnnn00111010
0000nnnn11111010
0000nnnn10000010
0000nnnn10010010
0000nnnn10100010
0000nnnn10110010
0000nnnn11000010
0000nnnn11010010
0000nnnn11100010
0000nnnn11110010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn00110011
0100nnnn01000011
0100nnnn00110010
0100nnnn11110010
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
Execution
States
T Bit
2
2
2
2
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
2
2
2
2
2
2
2
2
2

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