Hitachi SH7750 Programming Manual page 265

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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qNaN
sNaN
}
}
void normal_fcnvds(int m, float *FPUL)
{
int sign;
float abs;
union {
float f;
int l;
}
dstf,tmpf;
union {
double d;
int l[2];
}
dstd;
dstd.d = DR[m>>1];
if(dstd.l[1] & 0x1fffffff)) set_I();
if(FPSCR_RM == 1) dstd.l[1] &= 0xe0000000; /* round toward zero*/
dstf.f = dstd.d;
check_single_exception(FPUL, dstf.f);
}
FCNVDS Special Cases
FRn
FCNVDS(FRn FPUL) FCNVDS
Note: When DN = 1, the value of a denormalized number is treated as 0.
Possible Exceptions:
• FPU error
• Invalid operation
• Overflow
• Underflow
• Inexact
:
*FPUL = 0x7fbfffff; break;
:
set_V();
if((FPSCR & ENABLE_V) == 0) *FPUL = 0x7fbfffff;
else fpu_exception_trap();
+NORM
–NORM
FCNVDS
+0
–0
+INF
+0
–0
+INF
Rev. 2.0, 03/99, page 251 of 396
break;
–INF
qNaN
sNaN
–INF
qNaN
Invalid

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