Fmov - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.38

FMOV

Floating-Point
Transfer
PR
Format
1
1. FMOV XDm,@Rn
1
2. FMOV @Rm,XDn
1
3. FMOV @Rm+,XDn
1
4. FMOV XDm,@-Rn
5. FMOV @(R0,Rm),XDn (R0+Rm) → XDn
1
6. FMOV XDm,@(R0,Rn) XDm → (R0+Rn)
1
1
7. FMOV XDm,XDn
1
8. FMOV XDm,DRn
1
9. FMOV DRm,XDn
Description
1. This instruction transfers XDm contents to memory at address indicated by Rn.
2. This instruction transfers contents of memory at address indicated by Rm to XDn.
3. This instruction transfers contents of memory at address indicated by Rm to XDn, and adds 8
to Rm.
4. This instruction subtracts 8 from Rn, and transfers XDm contents to memory at address
indicated by resulting Rn value.
5. This instruction transfers contents of memory at address indicated by (R0 + Rm) to XDn.
6. This instruction transfers XDm contents to memory at address indicated by (R0 + Rn).
7. This instruction transfers XDm contents to XDn.
8. This instruction transfers XDm contents to DRn.
9. This instruction transfers DRm contents to XDn.
Floating-point
MOVe extension
Summary of
Operation
XRm → (Rn)
(Rm) → XDn
(Rm) → XDn,Rm+=8 1111nnn1mmmm1001 1
Rn-=8,XDm → (Rn)
XDm → XDn
XDm → DRn
DRm → XDn
Floating-Point Instruction
Instruction Code
1111nnnnmmm11010 1
1111nnn1mmmm1000 1
1111nnnnmmm11011 1
1111nnn1mmmm0110 1
1111nnnnmmm10111 1
1111nnn1mmm11100 1
1111nnn0mmm11100 1
1111nnn1mmm01100 1
Rev. 2.0, 03/99, page 275 of 396
Execution
States
T Bit

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