Hitachi SH7750 Programming Manual page 321

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Operation
LDTLB( )
/*LDTLB */
{
TLB[MMUCR. URC] .ASID=PTEH & 0x000000FF;
TLB[MMUCR. URC] .VPN=(PTEH & 0xFFFFFC00)>>10;
TLB[MMUCR. URC] .PPN=(PTEH & 0x1FFFFC00)>>10;
TLB[MMUCR. URC] .SZ=(PTEL & 0x00000080)>>6 |
(PTEL & 0x00000010)>>4;
TLB[MMUCR. URC] .SH=(PTEH & 0x00000002)>>1;
TLB[MMUCR. URC] .PR=(PTEH & 0x00000060)>>5;
TLB[MMUCR. URC] .WT=(PTEH & 0x00000001);
TLB[MMUCR. URC] .C=(PTEH & 0x00000008)>>3;
TLB[MMUCR. URC] .D=(PTEH & 0x00000004)>>2;
TLB[MMUCR. URC] .V=(PTEH & 0x00000100)>>8;
TLB[MMUCR. URC] .SA=(PTEA & 0x00000007);
TLB[MMUCR. URC] .TC=(PTEA & 0x00000008)>>3;
PC+=2;
}
Example
MOV
@R0,R1
MOV
R1,@R2
LDTLB
;Load page table entry (upper) into R1
;Load R1 into PTEH; R2 is PTEH address (H'FF000000)
;Load PTEH, PTEL, PTEA registers into TLB
Rev. 2.0, 03/99, page 307 of 396

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