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Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module
related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral
module related pins in the input or high-impedance state.
For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.
Bit 5: PPU
0
1
Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the
on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set
to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA
transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again.
Bit 4: MSTP4
0
1
Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication
interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is
stopped when the MSTP3 bit is set to 1.
Bit 3: MSTP3
0
1
Bit 2—Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit (TMU)
among the on-chip peripheral modules. The clock supply to the TMU is stopped when the MSTP2
bit is set to 1.
Bit 2: MSTP2
0
1
Rev. 2.0, 03/99, page 180 of 396
Description
Peripheral module related pin pull-up resistors are on
Peripheral module related pin pull-up resistors are off
Description
DMAC operates
DMAC clock supply is stopped
Description
SCIF operates
SCIF clock supply is stopped
Description
TMU operates
TMU clock supply is stopped
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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