Pref - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.74

PREF

Prefetch to Data
Cache
Format
PREF @Rn
Description
This instruction reads a 32-byte data block starting at a 32-byte boundary into the operand cache.
The lower 5 bits of the address specified by Rn are masked to zero.
This instruction does not generate address-related errors. In the event of an error, the PREF
instruction is treated as an NOP (no operation) instruction.
Operation
PREF(int n) /* PREF */
{
PC+=2;
}
Example
MOV.L
PREF
.align 32
SOFT_PF:
.data.l
.data.l
.data.l
.data.l
.data.l
.data.l
.data.l
.data.l
Rev. 2.0, 03/99, page 344 of 396
PREFetch data to cache
Summary of Operation
Prefetch cache block
#SOFT_PF,R1
@R1
H'12345678
H'9ABCDEF0
H'AAAA5555
H'5555AAAA
H'11111111
H'22222222
H'33333333
H'44444444
Data Transfer Instruction
Instruction Code
0000nnnn10000011
;R1 address is SOFT_PF
;Load SOFT_PF data into on-chip cache
Execution
States
T Bit

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