Table of Contents
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Table 1.1
SH7750 Features (cont)
Item
Clock pulse
generator (CPG)
Memory
management
unit (MMU)
Rev. 2.0, 03/99, page 4 of 396
Features
•
Choice of main clock: 1/2, 1, 3, or 6 times EXTAL
•
Clock modes:
CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock:
maximum 200 MHz
Bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock: maximum
100 MHz
Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock:
maximum 50 MHz
•
Power-down modes
Sleep mode
Standby mode
Module standby function
•
Single-channel watchdog timer
•
4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
•
Single virtual mode and multiple virtual memory mode
•
Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
•
4-entry fully-associative TLB for instructions
•
64-entry fully-associative TLB for instructions and operands
•
Supports software-controlled replacement and random-counter
replacement algorithm
•
TLB contents can be accessed directly by address mapping
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