Hitachi SH7750 Programming Manual page 293

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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}
break;
case PZERO:
case NZERO: switch (data_type_of(n)){
case PINF:
case NINF:
default:
}
break;
case PINF :
case NINF : switch (data_type_of(n)){
}
break;
}
}
FMUL Special Cases
FRm,DRm
NORM
NORM
MUL
+0
0
–0
+INF
INF
–INF
DENORM
qNaN
sNaN
Note: When DN = 1, the value of a denormalized number is treated as 0.
Possible Exceptions:
• FPU error
• Invalid operation
• Overflow
• Underflow
• Inexact
invalid(n); break;
zero(n,sign_of(m)^sign_of(n));break;
case PZERO:
case NZERO: invalid(n);
default:
inf(n,sign_of(m)^sign_of(n));break
+0
–0
0
+0
–0
–0
+0
Invalid
break;
FRn,DRn
+INF
–INF
INF
Invalid
+INF
–INF
–INF
+INF
DENORM
qNaN
Error
qNaN
Rev. 2.0, 03/99, page 279 of 396
sNaN
Invalid

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