Hitachi SH7750 Programming Manual page 166

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10. OCBI: 1 issue cycle
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11. OCBP, OCBWB: 1 issue cycle
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12. MOVCA.L: 1 issue cycle
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13. TRAPA: 7 issue cycles
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14. CR definition: 1 issue cycle
LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR
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15. LDC to GBR: 3 issue cycles
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16. LDC to SR: 4 issue cycles
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17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
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18. LDC.L to GBR: 3 issue cycles
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Rev. 2.0, 03/99, page 152 of 396
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Figure 8.2 Instruction Execution Patterns (cont)
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