Hitachi SH7750 Programming Manual page 13

10.90 SHLRn ........ n bits SHift Logical Right .......................Shift Instruction..................... 365
10.91 SLEEP ......... SLEEP ....................................................System Control Instruction ... 367
10.92 STC ............. STore Control register ............................System Control Instruction ... 368
10.93 STS .............. STore System register .............................System Control Instruction ... 373
10.94 STS .............. STore from FPU System register ............System Control Instruction ... 375
10.95 SUB ............. SUBtract binary ......................................Arithmetic Instruction ........... 377
10.96 SUBC .......... SUBtract with Carry ...............................Arithmetic Instruction ........... 378
10.97 SUBV .......... SUBtract with (V flag) underflow check Arithmetic Instruction ........... 379
10.98 SWAP ......... SWAP register halves .............................Data Transfer Instruction ...... 381
10.99 TAS ............. Test And Set ...........................................Logical Instruction ................ 383
10.100 TRAPA ........ TRAP Always .........................................System Control Instruction ... 385
10.101 TST ............. TeST logical ...........................................Logical Instruction ................ 386
10.102 XOR ............ eXclusive OR logical ..............................Logical Instruction ................ 388
10.103 XTRCT ........ eXTRaCT ...............................................Data Transfer Instruction ...... 390
Appendix A Address List
Appendix B Instruction Prefetch Side Effects
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Rev. 2.0, 03/99, page xiii of 13