Priority Order With Multiple Exceptions - Hitachi SH7750 Programming Manual

5.6.4

Priority Order with Multiple Exceptions

With some instructions, such as instructions that make two accesses to memory, and the
indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple
exceptions occur. Care is required in these cases, as the exception priority order differs from the
normal order.
1. Instructions that make two accesses to memory
With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS
instructions, two data transfers are performed by a single instruction, and an exception will be
detected for each of these data transfers. In these cases, therefore, the following order is used
to determine priority.
a. Data address error in first data transfer
b. TLB miss in first data transfer
c. TLB protection violation in first data transfer
d. Initial page write exception in first data transfer
e. Data address error in second data transfer
f. TLB miss in second data transfer
g. TLB protection violation in second data transfer
h. Initial page write exception in second data transfer
2. Indivisible delayed branch instruction and delay slot instruction
As a delayed branch instruction and its associated delay slot instruction are indivisible, they
are treated as a single instruction. Consequently, the priority order for exceptions that occur in
these instructions differs from the usual priority order. The priority order shown below is for
the case where the delay slot instruction has only one data transfer.
a. The delayed branch instruction is checked for priority levels 1 and 2.
b. The delay slot instruction is checked for priority levels 1 and 2.
c. A check is performed for priority level 3 in the delayed branch instruction and priority
level 3 in the delay slot instruction. (There is no priority ranking between these two.)
d. A check is performed for priority level 4 in the delayed branch instruction and priority
level 4 in the delay slot instruction. (There is no priority ranking between these two.)
If the delay slot instruction has a second data transfer, two checks are performed in step b, as in
1 above.
If the accepted exception (the highest-priority exception) is a delay slot instruction re-
execution type exception, the branch instruction PR register write operation (PC → PR
operation performed in BSR, BSRF, JSR) is inhibited.
Rev. 2.0, 03/99, page 114 of 396