Fsub - Hitachi SH7750 Programming Manual

10.45

FSUB

Floating-Point
Subtraction
PR Format
0 FSUB FRm,FRn
FSUB DRm,DRn DRn-DRm → DRn
1
Description
When FPSCR.PR = 0: Arithmetically subtracts the single-precision floating-point number in FRm
from the single-precision floating-point number in FRn, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically subtracts the double-precision floating-point number in
DRm from the double-precision floating-point number in DRn, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FSUB (int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else if((data_type_of(m) == DENORM) ||
(data_type_of(n) == DENORM)) set_E();
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case NORM:
case PZERO:
case NZERO: register_copy(m,n); FR[n] = -FR[n];break;
default:
Floating-point
SUBtract
Summary of Operation
FRn-FRm → FRn
normal_faddsub(m,n,SUB); break;
break;
Floating-Point Instruction
Instruction Code
1111nnnnmmmm0001 1
1111nnn0mmm00001 6
Rev. 2.0, 03/99, page 287 of 396
Execution
States T Bit
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