Hitachi SH7750 Programming Manual page 212

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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}
void clear_cause () {FPSCR &= ~CAUSE;}
void set_E() {FPSCR |= SET_E; fpu_exception_trap();}
void set_V() {FPSCR |= SET_V;}
void set_Z() {FPSCR |= SET_Z;}
void set_O() {FPSCR |= SET_O;}
void set_U() {FPSCR |= SET_U;}
void set_I() {FPSCR |= SET_I;}
void invalid(int n)
{
set_V();
if((FPSCR & ENABLE_V) == 0 qnan(n);
else
fpu_exception_trap();
}
void dz(int n,sign)
{
set_Z();
if((FPSCR & ENABLE_Z) == 0 inf(n,sign);
else
fpu_exception_trap();
}
void zero(int n,sign)
{
if(sign == 0)
else
if (FPSCR_PR==1) FR_HEX [n+1] = 0x00000000;
}
void inf(int n,sign) {
if (FPSCR_PR==0) {
if(sign == 0)
else
}else {
if(sign == 0)
else
}
}
Rev. 2.0, 03/99, page 198 of 396
FR_HEX [n]
= 0x00000000;
FR_HEX [n]
= 0x80000000;
FR_HEX [n]
= 0x7f800000;
FR_HEX [n]
= 0xff800000;
FR_HEX [n]
= 0x7ff00000;
FR_HEX [n]
= 0xfff00000;
FR_HEX [n+1] = 0x00000000;

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