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Hitachi SH7750 Programming Manual page 169

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series

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40. Double-precision FCMP: 2 issue cycles

FCMP/EQ,FCMP/GT

41. Double-precision FDIV/SQRT: 1 issue cycle

42. FIPR: 1 issue cycle

43. FTRV: 1 issue cycle

: Cannot overlap a stage of the same kind, except when two instructions are

executed in parallel.

: Locks D-stage

: Register read only

: Locks, but no operation is executed.

: Can overlap another f1, but not another F1.

Figure 8.2 Instruction Execution Patterns (cont)

Rev. 2.0, 03/99, page 155 of 396