Hitachi SH7750 Programming Manual page 248

Example 2
TST R0,R0
BT ZERO_DIV
CMP/HS R0,R1
BT OVER_DIV
DIV0U
.arepeat 32
ROTCL R2
DIV1 R0,R1
.aendr
ROTCL R2
Example 3
SHLL16 R0
EXTS.W R1,R1
XOR R2,R2
MOV R1,R3
ROTCL R3
SUBC R2,R1
DIV0S R0,R1
.arepeat 16
DIV1 R0,R1
.aendr
EXTS.W R1,R1
ROTCL R1
ADDC R2,R1
EXTS.W R1,R1
Rev. 2.0, 03/99, page 234 of 396
; R1:R2 (64 bits) ÷ R0 (32 bits) = R2 (32 bits); unsigned
;Check for division by zero
;
;Check for overflow
;
;Flag initialization
;
;Repeat 32 times
;
;
;R2 = quotient
;R1 (16 bits) ÷ R0 (16 bits) = R1 (16 bits); signed
;Set divisor in upper 16 bits, clear lower 16 bits to 0
;Dividend sign-extended to 32 bits
;R2 = 0
;
;
;If dividend is negative, subtract 1
;Flag initialization
;
;Repeat 16 times
;
;
;R1 = quotient (one's complement notation)
;If MSB of quotient is 1, add 1 to convert to two's complement notation
;R1 = quotient (two's complement notation)