Hitachi SH7750 Programming Manual page 270

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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}
tmpx;
if(FPSCR_PR == 0) {
tmpf.f = FR[n]; /* save destination value */
dstf.f /= FR[m]; /* round toward nearest or even */
tmpd.d = dstf.f; /* convert single to double */
tmpd.d *= FR[m];
if(tmpf.f != tmpd.d) set_I();
if((tmpf.f < tmpd.d) && (SPSCR_RM == 1))
dstf.l -= 1; /* round toward zero */
check_single_exception(&FR[n], dstf.f);
}else {
tmpd.d = DR[n>>1]; /* save destination value */
dstd.d /= DR[m>>1]; /* round toward nearest or even */
tmpx.x = dstd.d; /* convert double to int double */
tmpx.x *= DR[m>>1];
if(tmpd.d != tmpx.x) set_I();
if((tmpd.d < tmpx.x) && (SPSCR_RM == 1)) {
dstd.l[1] -= 1; /* round toward zero */
if(dstd.l[1] == 0xffffffff) dstd.l[0] -= 1;
}
check_double_exception(&DR[n>>1], dstd.d);
}
}
FDIV Special Cases
FRm,DRm
NORM
NORM
DIV
+0
DZ
–0
+INF
0
–INF
DENORM
qNaN
sNaN
Note: When DN = 1, the value of a denormalized number is treated as 0.
Rev. 2.0, 03/99, page 256 of 396
FRn,DRn
+0
–0
0
Invalid
+0
–0
–0
+0
+INF
–INF
DENORM
INF
+INF
–INF
–INF
+INF
Invalid
qNaN
Error
DZ
Error
qNaN
sNaN
Invalid

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