Hitachi SH7750 Programming Manual page 374

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Operation
SHLD(int m,n)/*SHLD Rm,Rn */
{
int sgn = R[m] & 0x80000000;
if (sgn == 0)
else if ((R[m] & 0x1F) == 0)
else
PC+=2;
}
Example
SHLD
R1, R2
SHLD
R3, R4
Rev. 2.0, 03/99, page 360 of 396
R[n] <<= (R[m] & 0x1F);
R[n] = 0;
R[n]=(unsigned)R[n] >> ((~R[m] & 0x1F)+1);
;Before execution R1 = H'FFFFFFEC, R2 = H'80180000
;After execution
;Before execution R3 = H'00000014, R4 = H'FFFFF801
;After execution
R1 = H'FFFFFFEC, R2 = H'00000801
R3 = H'00000014, R4 = H'80100000

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