Hitachi SH7750 Programming Manual page 302

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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}
case PZERO: break;
case NZERO: switch (data_type_of(n)){
case NZERO: zero(n,0); break;
default:
}
case PINF: switch (data_type_of(n)){
case PINF:
default:
}
break;
case NINF: switch (data_type_of(n)){
case NINF:
default:
}
}
}
FSUB Special Cases
FRm,DRm
NORM
NORM
SUB
+0
–0
+INF
–INF
–INF
+INF
DENORM
qNaN
sNaN
Note: When DN = 1, the value of a denormalized number is treated as 0.
Possible Exceptions:
• FPU error
• Invalid operation
• Overflow
• Underflow
• Inexact
Rev. 2.0, 03/99, page 288 of 396
break;
break;
break;
invalid(n);
inf(n,1);
invalid(n);
inf(n,0);
break;
FRn,DRn
+0
–0
–0
+0
Invalid
break;
break;
break;
break;
+INF
–INF
DENORM
+INF
–INF
Invalid
qNaN
Error
qNaN
sNaN
Invalid

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