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VA is
in P4 area
Access prohibited
No
Search UTLB
Match?
No
Instruction TLB
miss exception
Instruction TLB protection
violation exception
Figure 3.11 Flowchart of Memory Access Using ITLB
Rev. 2.0, 03/99, page 44 of 396
Instruction access to virtual address (VA)
VA is
VA is
in P2 area
in P1 area
0
CCR.ICE?
1
VPNs match
and V = 1
Yes
Hardware ITLB
miss handling
Yes
Record in ITLB
0
and CCR.ICE = 1
No
MMUCR.AT = 1
SH = 0
No
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match
No
and ASIDs match and
Only one
entry matches
SR.MD?
0 (User)
PR?
1
C = 1
No
Yes
Cache access
VA is in P0, U0,
or P3 area
Yes
Yes
V = 1
Yes
No
Yes
1 (Privileged)
Instruction TLB
multiple hit exception
Memory access
(Non-cacheable)
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