Table of Contents
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Table 1.1
SH7750 Features (cont)
Item
Cache memory
Interrupt controller
(INTC)
User break
controller (UBC)
Features
•
Instruction cache (IC)
8 kbytes, direct mapping
256 entries, 32-byte block length
Normal mode (8-kbyte cache)
Index mode
•
Operand cache (OC)
16 kbytes, direct mapping
512 entries, 32-byte block length
Normal mode (16-kbyte cache)
Index mode
RAM mode (8-kbyte cache + 8-kbyte RAM)
Choice of write method (copy-back or write-through)
•
Single-stage copy-back buffer, single-stage write-through buffer
•
Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
•
Store queue (32 bytes × 2 entries)
•
Five independent external interrupts (NMI, IRL3 to IRL0)
•
15-level signed external interrupts: IRL3 to IRL0
•
On-chip peripheral module interrupts: Priority level can be set for each
module
•
Supports debugging by means of user break interrupts
•
Two break channels
•
Address, data value, access type, and data size can all be set as break
conditions
•
Supports sequential break function
Rev. 2.0, 03/99, page 5 of 396
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