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10.8
BRAF
Unconditional Branch
Format
BRAF Rn
Description
This is an unconditional branch instruction. The branch destination is address (PC + 4 + Rn). The
branch destination address is the result of adding 4 plus the 32-bit contents of general register Rn
to PC.
Notes
As this is a delayed branch instruction, the instruction following this instruction is executed before
the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation
BRAF(int n)
{
unsigned int temp;
temp=PC;
PC=PC+4+R[n];
Delay_Slot(temp+2);
}
Example
MOV.L #(TRGET-BRAF_PC),R0
BRAF
R0
ADD
R0,R1
BRAF_PC:
NOP
TRGET:
BRAnch Far
Summary of Operation
PC+4+Rn → PC
/* BRAF Rn */
Instruction Code
0000nnnn00100011 2
;Set displacement.
;Branch to TRGET.
;ADD executed before branch.
;
;← BRAF instruction branch destination
Branch Instruction
Delayed Branch Instruction
Execution
States
Rev. 2.0, 03/99, page 213 of 396
T Bit
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