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10.10
BSRF
Branch to Subroutine Procedure
Format
BSRF Rn
Description
This instruction branches to address (PC + 4 + Rn), and stores address (PC + 4) in PR. The PC
source value is the BSRF instruction address. The branch destination address is the result of
adding the 32-bit contents of general register Rn to PC + 4.
Notes
As this is a delayed branch instruction, the instruction following this instruction is executed before
the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation
BSRF(int n)
{
unsigned int temp;
temp=PC;
PR=PC+4;
PC=PC+4+R[n];
Delay_Slot(tmp+2);
}
Rev. 2.0, 03/99, page 216 of 396
Branch to SubRoutine Far
Summary of Operation
PC+4 → PR,
PC+4+Rn → PC
/* BSRF Rn */
Branch Instruction
Delayed Branch Instruction
Instruction Code
0000nnnn00000011 2
Execution
States
T Bit
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