Hitachi SH7750 Programming Manual page 155

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Table 7.6
Shift Instructions
Instruction
ROTL
Rn
ROTR
Rn
ROTCL
Rn
ROTCR
Rn
SHAD
Rm,Rn
SHAL
Rn
SHAR
Rn
SHLD
Rm,Rn
SHLL
Rn
SHLR
Rn
SHLL2
Rn
SHLR2
Rn
SHLL8
Rn
SHLR8
Rn
SHLL16
Rn
SHLR16
Rn
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
When Rn ≥ 0, Rn << Rm → Rn
When Rn < 0, Rn >> Rm →
[MSB → Rn]
T ← Rn ← 0
MSB → Rn → T
When Rn ≥ 0, Rn << Rm → Rn
When Rn < 0, Rn >> Rm →
[0 → Rn]
T ← Rn ← 0
0 → Rn → T
Rn << 2 → Rn
Rn >> 2 → Rn
Rn << 8 → Rn
Rn >> 8 → Rn
Rn << 16 → Rn
Rn >> 16 → Rn
Instruction Code
0100nnnn00000100 —
0100nnnn00000101 —
0100nnnn00100100 —
0100nnnn00100101 —
0100nnnnmmmm1100 —
0100nnnn00100000 —
0100nnnn00100001 —
0100nnnnmmmm1101 —
0100nnnn00000000 —
0100nnnn00000001 —
0100nnnn00001000 —
0100nnnn00001001 —
0100nnnn00011000 —
0100nnnn00011001 —
0100nnnn00101000 —
0100nnnn00101001 —
Rev. 2.0, 03/99, page 141 of 396
Privileged
T Bit
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB

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