Hitachi SH7750 Programming Manual page 160

Table 7.10 Floating-Point Double-Precision Instructions
Instruction
FABS DRn
FADD DRm,DRn
FCMP/EQ DRm,DRn
FCMP/GT DRm,DRn
FDIV DRm,DRn
FCNVDS DRm,FPUL
FCNVSD FPUL,DRn
FLOAT FPUL,DRn
FMUL DRm,DRn
FNEG DRn
FSQRT DRn
FSUB DRm,DRn
FTRC DRm,FPUL
Table 7.11 Floating-Point Control Instructions
Instruction
LDS Rm,FPSCR
LDS Rm,FPUL
LDS.L @Rm+,FPSCR
LDS.L @Rm+,FPUL
STS FPSCR,Rn
STS FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Rev. 2.0, 03/99, page 146 of 396
Operation
DRn & H'7FFF FFFF FFFF
FFFF → DRn
DRn + DRm → DRn
When DRn = DRm, 1 → T
Otherwise, 0 → T
When DRn > DRm, 1 → T
Otherwise, 0 → T
DRn /DRm → DRn
double_to_ float[DRm] → FPUL 1111mmm010111101 —
float_to_ double [FPUL] → DRn 1111nnn010101101 —
(float)FPUL → DRn
DRn *DRm → DRn
DRn ^ H'8000 0000 0000 0000
→ DRn
√DRn → DRn
DRn – DRm → DRn
(long) DRm → FPUL
Operation
Rm → FPSCR
Rm → FPUL
(Rm) → FPSCR, Rm+4 → Rm
(Rm) → FPUL, Rm+4 → Rm
FPSCR → Rn
FPUL → Rn
Rn – 4 → Rn, FPSCR → (Rn)
Rn – 4 → Rn, FPUL → (Rn)
Instruction Code
1111nnn001011101 —
1111nnn0mmm00000 —
1111nnn0mmm00100 —
1111nnn0mmm00101 —
1111nnn0mmm00011 —
1111nnn000101101 —
1111nnn0mmm00010 —
1111nnn001001101 —
1111nnn001101101 —
1111nnn0mmm00001 —
1111mmm000111101 —
Instruction Code
0100mmmm01101010 —
0100mmmm01011010 —
0100mmmm01100110 —
0100mmmm01010110 —
0000nnnn01101010 —
0000nnnn01011010 —
0100nnnn01100010 —
0100nnnn01010010 —
Privileged T Bit
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Comparison
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Comparison
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Privileged T Bit
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