Ocbwb - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
Hide thumbs Also See for SH7750:
Table of Contents

Advertisement

10.72

OCBWB

Cache Block Write-Back
Format
OCBWB @Rn
Description
This instruction accesses data using the contents indicated by effective address Rn. If the cache is
hit and there is unwritten information (U bit = 1), the corresponding cache block is written back to
external memory and that block is cleaned (the U bit is cleared to 0). In other cases (i.e. in the case
of a cache miss or an access to a non-cache area, or if the block is already clean), no operation is
performed.
Operation
OCBWB(int n)
{
if(is_dirty_block(R[n]))
PC+=2;
}
Possible Exceptions:
• Data TLB miss exception
• Data TLB protection violation exception
• Address error
Note that the above exceptions are generated even if OCBWB does not operate.
Operand Cache Block
Write Back
Summary of Operation
Operand cache block write-
back
/* OCBWB @Rn */
Data Transfer Instruction
Instruction Code
0000nnnn10110011 1
write_back(R[n]);
Rev. 2.0, 03/99, page 341 of 396
Execution
States
T Bit

Advertisement

Table of Contents
loading

Table of Contents