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Hitachi SH7750 Programming Manual page 180

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series

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(h) Resource conflict

FMAC FR0,FR8,FR9

FMAC FR0,FR10,FR11

FMAC FR0,FR12,FR13

FADD FR15,FR4

LDS.L @R15+,PR

FADD DR0,DR2

MAC.W @R1+,@R2+

Rev. 2.0, 03/99, page 166 of 396

1 cycle/issue

1 stall cycle

3 stall cycles

3 stall cycles

Figure 8.3 Examples of Pipelined Execution (cont)

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5 stall cycles

f1 stage can overlap preceding f1,

but F1 cannot overlap f1.

2 stall cycles

F1 stage locked for 1 cycle

1 stall cycle (F1 stage resource conflict)