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•
RM: Rounding mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
• Bits 22 to 31: Reserved
These bits are always read as 0, and should only be written with 0.
Notes: The following functions have been added to the FPU of the SH7750 (not provided in the
FPU of the SH7718):
1. The FR, SZ, and PR bits have been added.
2. Exception O (overflow), U (underflow), and I (inexact) bits have been added to the
cause, enable, and flag fields.
3. An exception E (FPU error) bit has been added to the cause field.
6.3.3
Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL
register is a system register, and is accessed from the CPU side by means of LDS and STS
instructions. For example, to convert the integer stored in general register R1 to a single-precision
floating-point number, the processing flow is as follows:
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
6.4
Rounding
In a floating-point instruction, rounding is performed when generating the final operation result
from the intermediate result. Therefore, the result of combination instructions such as FMAC,
FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB,
or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL.
There are two rounding methods, the method to be used being determined by the RM field in
FPSCR.
• RM = 00: Round to Nearest
• RM = 01: Round to Zero
Round to Nearest: The value is rounded to the nearest expressible value. If there are two nearest
expressible values, the one with an LSB of 0 is selected.
Rev. 2.0, 03/99, page 124 of 396
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