Hitachi SH7750 Programming Manual page 409

Table A.1 Address List (cont)
Module Register P4 Address
TMU TCOR1 H'FFD8 0014 H'1FD8 0014 32
TMU TCNT1 H'FFD8 0018 H'1FD8 0018 32
TMU TCR1 H'FFD8 001C H'1FD8 001C 16
TMU TCOR2 H'FFD8 0020 H'1FD8 0020 32
TMU TCNT2 H'FFD8 0024 H'1FD8 0024 32
TMU TCR2 H'FFD8 0028 H'1FD8 0028 16
TMU TCPR2 H'FFD8 002C H'1FD8 002C 32
SCI SCSMR1 H'FFE0 0000 H'1FE0 0000 8
SCI SCBRR1 H'FFE0 0004 H'1FE0 0004 8
SCI SCSCR1 H'FFE0 0008 H'1FE0 0008 8
SCI SCTDR1 H'FFE0 000C H'1FE0 000C 8
SCI SCSSR1 H'FFE0 0010 H'1FE0 0010 8
SCI SCRDR1 H'FFE0 0014 H'1FE0 0014 8
SCI SCSCMR1 H'FFE0 0018 H'1FE0 0018 8
SCI SCSPTR1 H'FFE0 001C H'1FE0 001C 8
SCIF SCSMR2 H'FFE8 0000 H'1FE8 0000 16
SCIF SCBRR2 H'FFE8 0004 H'1FE8 0004 8
SCIF SCSCR2 H'FFE8 0008 H'1FE8 0008 16
SCIF SCFTDR2 H'FFE8 000C H'1FE8 000C 8
SCIF SCFSR2 H'FFE8 0010 H'1FE8 0010 16
SCIF SCFRDR2 H'FFE8 0014 H'1FE8 0014 8
SCIF SCFCR2 H'FFE8 0018 H'1FE8 0018 16
SCIF SCFDR2 H'FFE8 001C H'1FE8 001C 16
SCIF SCSPTR2 H'FFE8 0020 H'1FE8 0020 16
SCIF SCLSR2 H'FFE8 0024 H'1FE8 0024 16
Hitachi- SDIR H'FFF0 0000 H'1FF0 0000 16
UDI
Hitachi- SDDR H'FFF0 0008 H'1FF0 0008 32
UDI
Notes: 1. With control registers, the above addresses in the physical page number field can be
accessed by means of a TLB setting. When these addresses are referenced directly
without using the TLB, operations are limited.
Area 7 Power-On
1
Address* Size Reset
H'FFFF FFFF H'FFFF FFFF Held
H'FFFF FFFF H'FFFF FFFF Held
H'0000
H'FFFF FFFF H'FFFF FFFF Held
H'FFFF FFFF H'FFFF FFFF Held
H'0000
Held
H'00
H'FF
H'00
H'FF
H'84
H'00
H'00
H'00*
H'0000
H'FF
H'0000
Undefined
H'0060
Undefined
H'0000
H'0000
H'0000*
H'0000
H'FFFF*
Held
Manual
Reset Sleep Standby
H'0000 Held
H'0000 Held
Held Held
H'00 Held
H'FF Held
H'00 Held
H'FF Held
H'84 Held
H'00 Held
H'00 Held
2 2
H'00* Held
H'0000 Held
H'FF Held
H'0000 Held
Undefined Held
H'0060 Held
Undefined Held
H'0000 Held
H'0000 Held
2 2
H'0000* Held
H'0000 Held
2
Held Held
Held Held
Rev. 2.0, 03/99, page 395 of 396
Synchro-
nization
Clock
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
H'00 Pclk
H'FF Pclk
H'00 Pclk
H'FF Pclk
H'84 Pclk
H'00 Pclk
H'00 Pclk
2
H'00* Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk