Div0U - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
Hide thumbs Also See for SH7750:
Table of Contents

Advertisement

10.18

DIV0U

Initialization for Unsigned Division
Format
DIV0U
Description
This instruction performs initial settings for unsigned division. This instruction is followed by a
DIV1 instruction that executes 1-digit division, for example, and repeated divisions are executed
to find the quotient. See the description of the DIV1 instruction for details.
Operation
DIV0U( )
{
M=Q=T=0;
PC+=2;
}
Example
See the examples for the DIV1 instruction.
Rev. 2.0, 03/99, page 230 of 396
DIVide (step 0) as Unsigned
Summary of Operation
0 → M/Q/T
/* DIV0U */
Arithmetic Instruction
Instruction Code
0000000000011001 1
Execution
States
T Bit
0

Advertisement

Table of Contents
loading

Table of Contents