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10.53
LDTLB
Load to TLB
Format
LDTLB
Description
This instruction loads the contents of the PTEH/PTEL/PTEA registers into the TLB (translation
lookaside buffer) specified by MMUCR.URC (random counter field in the MMC control register).
LDTLB is a privileged instruction, and can only be used in privileged mode. Use of this
instruction in user mode will cause an illegal instruction exception.
Notes
As this instruction loads the contents of the PTEH/PTEL/PTEA registers into a TLB, it should be
used either with the MMU disabled, or in the P1 or P2 virtual space with the MMU enabled (see
section 3, Memory Management Unit, for details). After this instruction is issued, there must be at
least one instruction between the LDTLB instruction and issuance of an instruction relating to
address to areas P0, U0, and P3 (i.e. BRAF, BSRF, JMP, JSR, RTS, or RTE).
Rev. 2.0, 03/99, page 306 of 396
LoaD PTEH/PTEL/PTEA
to TLB
Summary of Operation
PTEH/PTEL/PTEA → TLB
System Control Instruction
(Privileged Instruction)
Instruction Code
0000000000111000 1
Execution
States
T Bit
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