Shld - Hitachi SH7750 Programming Manual

10.86

SHLD

Dynamic Logical
Shift
Format
SHLD Rm, Rn
Description
This instruction logically shifts the contents of general register Rn. General register Rm specifies
the shift direction and the number of bits to be shifted.
Rn register contents are shifted to the left if the Rm register value is positive, and to the right if
negative. In a shift to the right, 0s are added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If
the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left
shift range is 0 to 31, and the right shift range, 1 to 32.
Rm
Rm
SHift Logical Dynamically
Summary of Operation
When Rm ≥ 0,
Rn << Rm → Rn
When Rm < 0,
Rn >> Rm → [0 → Rn]
0
MSB
0
MSB
0
Shift Instruction
Instruction Code
0100nnnnmmmm1101 1
LSB
LSB
Rev. 2.0, 03/99, page 359 of 396
Execution
States T Bit
—
0