Gestetner B130 Service Manual page 267

BLOCK DIAGRAM: PCBS AND COMPONENTS (B044/B045/B046)
SPC2
The machine's CPU utilizes a dual bus structure (CPU bus and DMA bus), and
includes DMA, DCR, JBIG, and energy-saver control circuits.
VPL (Video Processing LSI)
This chip implements video processing, utilizing the following internal blocks:
• VPM (Video Processing Module)
Implements scanning control and image processing.
• LIF (Laser Interface)
Implements printing control and image processing
CIOP (Communications and I/O Processing)
Implements communication and I/O control circuits. Runs at 9.83MHz (clock
signal supplied by the SPC2).
FROM (Flash ROM) – 2MB
The machine's program memory. Packaged in a 48-pin TSOP; 75ns access
time; runs at +2.7 to +3.6 V (+3VE). The memory content can be overwritten
from a flash memory card.
DRAM – 8MB
The machine's standard operating RAM packaged in a 54-pin TSOP; 100MHz
maximum clock speed; operates at +3.3V (+3VD). Allocated as follows: 6.0K for
page memory and (if applicable) ring buffer; 1M for fax SAF; 576K working
RAM; 256K line buffer, 128K ECM buffer, 128K OS, 64K text SAF. On B046
machines, the SAF backup circuit will maintain DRAM content for up to about 12
hours if power outage occurs while SAF data is being stored.
NOTE: If optional DIMM is installed, the allocations for page memory, ring
buffer, and fax SAF are different from the above, and 2.5 to 5.4K may
be allocated for sort SAF.
SRAM – 128K
Stores users settings and usage data. Packaged in a 32-pin TSOP; 70ns
access time; runs at +2.7 to +3.6 V (+3V BAT). On-board battery backup
maintains memory content while power is off.
3V/5V Converter
Interface between the 3V output by the FCU and the 5V used by service flash
card.
Energy-Saver Switching
Controls low-power mode switching
B129 Series/B044 Series
CÓPIA NÃO CONTROLADA
6-10
CÓPIA NÃO CONTROLADA
SM