Dma Fly-By Transfer (I/O -> Memory) - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series

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CHAPTER 4 EXTERNAL BUS INTERFACE

4.5.10 DMA Fly-By Transfer (I/O -> Memory)

This section shows the operation timing for DMA fly-by transfer (I/O -> memory).

■ Operation Timing for DMA Fly-By Transfer (I/O -> Memory)

Figure 4.5-10 shows the operation timing for (TYP3 to TYP0=0000

This timing chart shows a case in which a wait is not set on the memory side.

Figure 4.5-10 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)

Setting "1" for the HLD bit of the IOWR0 to IOWR3 registers enables the I/O read cycle to be

extended by one cycle.

Setting bits IW3 to IW0 of the IOWR0 to IOWR3 registers enables 0 to 15 wait cycles to be

If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used

as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits).