Block Diagram Of Address Match Detection Function - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
21.2

Block Diagram of Address Match Detection Function

The address match detection module consists of the following blocks:
• Address latch
• Program address detection control status register (PACSR)
• Program address detection registers (PADR0/PADR1)
■ Block Diagram of Address Match Detection Function
Figure 21.2-1 shows the block diagram of the address match detection function.
Figure 21.2-1 Block Diagram of the Address Match Detection Function
Program address detection register 0
Program address detection register 1
PACSR
Reserved
Program address detection control status register ( PACSR)
Reserved: Always set to "0"
●
Address latch
The address latch stores the value of the address output to the internal data bus.
●
Program address detection control status register (PACSR)
The address detection control register enables or disables output of an interrupt at an address match.
●
Program address detection registers (PADR0, PADR1)
The detect address setting registers set the address that is compared with the value of the address latch.
Note:
The addresses of the Program address detection register are 1FF0
the RAM area. Therefore, the access to the RAM area should not be performed during the use of
this function (only MB90V330A).
CM44-10137-6E
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
Address latch
PADR0 (24bit)
PADR1 (24bit)
Reserved Reserved Reserved AD1E Reserved AD0E
FUJITSU MICROELECTRONICS LIMITED
21.2 Block Diagram of Address Match Detection Function
INT9 instruction
(INT9 interrupt
generation)
Reserved
to 1FF5 and are included in
H H
461